1. Field of the Invention
This invention relates generally to non-volatile memory devices having a floating gate such as an array of flash electrically erasable and programmable read-only memory (EEPROMs) devices. More particularly, the present invention relates to a new and novel method of achieving a narrow threshold voltage distribution after erase in a flash EEPROM.
2. Description of the Prior Art
One type of non-volatile memory device is referred to as "flash EEPROMs" which are both programmable and erasable electrically. In these flash memories, a plurality of one-transistor flash EEPROM cells may be formed on a P-type semiconductor substrate in which each is comprised of an N-type source region and an N-type drain region both formed integrally within the substrate. A relatively thin gate dielectric layer is interposed between a top surface of the substrate and a conductive polysilicon floating gate. A polysilicon control gate is insulatively supported above the floating gate by a second dielectric layer. A channel region in the substrate separates the source and drain regions.
In a conventional operation, in order to program a flash EEPROM cell high gate-to-drain voltage pulses are applied to the cell while the source thereof is grounded. For example, during programming multiple voltage pulses of approximately 10 V are each applied for about 2 or 3 .mu.S to the control gate while the drain voltage is set to +5.5 V and its source is grounded. The high gate-to-drain voltage pulses produce "hot" (high energy) electrons into the channel region near the drain region. These "hot" electrons are accelerated across the thin gate dielectric layer into the floating gate, thereby increasing the threshold voltage by three to five volts. The term "threshold" refers to a gate-to-source voltage that must be applied between the gate and the source of the cell in order to cause it to conduct.
In order to erase the flash EEPROM cell, relatively high negative gate-to-source voltage pulses are applied for a few tenths of a second to the cell. For example, during erase multiple voltage pulses of approximately -10 V are each applied to the control gate while the source voltage is set to +5.5 V and its drain is floating. The high negative gate-to-source voltage pulses cause the electrons to be extracted from the floating gate through the gate dielectric layer to the source region by way of Fowler-Norheim (F-N) tunneling, thereby reducing the threshold voltage of the cell.
As is generally well-known in the art, the threshold voltage of each single-transistor flash EEPROM cell after erase in the flash memory is variable. A large variation or wide distribution of the threshold voltages V.sub.T after erasure is one of the most considered problems in performance possessed by EEPROM devices. The distribution of the threshold voltages V.sub.T among the individual cells in the EEPROM array having floating-gate memory cells arrayed in rows and columns is caused by process variations, including local variations in the tunnel oxide thickness, the area of tunneling region, and the capacitive coupling ratio between the control gates and the floating gates as well as variations in the strengths of the erasing pulses.
If an unprogrammed flash EEPROM cell in the array of such cells is repeatedly erased under the above described conditions, the floating gate will eventually acquire a more positive potential so that the erase threshold voltage V.sub.T on a given column (bit line) will be less than zero. As a result, even with the control gate being grounded the cell will be conductive which causes column leakage so as to prevent the proper reading of any other cell in the column of the array containing this cell as well as making programming of other cells in the same column increasingly more difficult. This condition is generally referred to as "bit overerase" which is disadvantageous since the data programming characteristics of the memory cell is deteriorated so as to cause endurance failures. As used herein, the term "endurance" refers to the number of times the memory cell may be reprogrammed and erased. Consequently, the "bit overerase" condition significantly reduces the endurance of the memory cell.
There have been various techniques developed in the prior art of correcting the problem of overerased cells, but they all generally suffer from a number of drawbacks or introduce other problems. One such prior art correction technique for correcting overerased bits in an array of flash EEPROM memory cells is illustrated in FIG. 1. For the purposes of completeness, reference is made to a technical paper authored by Seiji Yamada et al. and entitled "A Self-Convergence Erase for NOR Flash EEPROM Using Avalanche Hot Carrier Injection," IEEE Transactions on Electron Devices, Vol. 43, No. 11, November 1996, pp. 1937-1941, which discusses in detail the over-erase correction method through channel hot-electron mechanism. As can be seen, a flash EEPROM array 10 is formed of a plurality of memory cells MC11 through MCnm arrayed in an n.times.m matrix on a single integrated circuit chip.
In other words, the memory array 10 includes approximately 128 thousand cells arranged in a regular matrix pattern of 2.sup.9 rows and 2.sup.8 columns. The memory cells MC11 through MC1m are arranged in the same row and have their selection terminals connected to the common word line WL.0.. Similarly, the cells MC21-MC2m are arranged in the same row and have their selection terminals connected to the common word line WL1. This is likewise done for each of the remaining rows in the array 10. Thus, the cells MCn1 through MCnm are arranged in the same row and have their selection terminals connected to the common word line WLn. In addition, the memory cells MC11 through MCn1 are arranged in the same column and have their data terminals connected to the common bit line BL.0.. Similarly, the cells MC12 through MCn2 are arranged in the same column and have their data terminals connected to the common bit line BL1. This is likewise done for each of the remaining columns in the array 10. Thus, the cells MC1m through MCnm are arranged in the same column and have their data terminals connected to the common bit line BLm.
Each of the memory cells MC11 through MCnm is comprised of one of the corresponding floating gate array transistors Q.sub.P11 through Q.sub.Pnm. The array transistors Q.sub.P11 -Q.sub.Pnm function as a memory transistor for storing data "1" or "0" therein. Each of the array transistors Q.sub.P11 -Q.sub.Pnm has its gate connected to one of the rows of word lines WL.0.-WLn, its drain connected to one of the columns of bit lines BL.0.-BLm, and its source connected to an array ground potential VSS.
After the flash memory array 10 has been erased, the prior art correction technique of correcting the overerased bits is performed on the array columns detected to have column leakage indicative of an overerased bit. Assume that the column or bit line BL1 was detected to contain an overerased bit. Then voltage pulses having a magnitude of approximately 3-5 volts and a width of approximately 100 .mu.S are applied to the bit line BL1 with the column leakage occurring while all of the word lines WL1-WLn, the common sources, and the substrate are grounded until the common leakage current is reduced.
This prior art overerased correction technique is only effective if the distribution of the erased threshold voltages V.sub.T is similar to the one illustrated in FIG. 2. The graph of FIG. 2 shows a threshold voltage distribution for the Flash EEPROM array having few overerased cells with a very negative V.sub.T (between -1 volts to 0 volts). The horizontal axis is the threshold voltage in volts, and the vertical axis represents the number of cells. Therefore, the curve 12 represents a plot of the number of cells in the array having a particular threshold voltage V.sub.T. It will be noted that most of the cells have not been overerased and thus have a positive threshold voltage and that only few cells have a negative threshold voltage. Further, the X's represent a few scattered well overerased cells. As a result, the application of the prior art correction technique will produce a threshold voltage distribution curve 14 of FIG. 3, where substantially all of the cells have a positive threshold voltage V.sub.T.
However, this prior art overerased correction technique suffers from the drawback of being ineffective in bringing back overerased cells having a slightly negative voltage V.sub.T, as depicted in FIG. 4, to a slightly positive value. As can be seen, the curve 16 represents a distribution where numerous cells have a slightly negative threshold voltage V.sub.T (just slightly below 0 volts). While each cell may contribute only 1 .mu.A of column leakage current, these cells together will have hundreds of microamps of leakage current. Consequently, the prior art overerased correction technique will be unable to reduce this column leakage current since all of the leaky bits have a threshold voltage slightly below 0 volts.
Accordingly, there has arisen a need to provide a new and novel method for correcting or bringing back overerased memory cells having either a very negative threshold voltage or a slightly negative threshold voltage to a positive value in an array of flash EEPROM memory cells after erase. The present invention represents a significant improvement over the aforementioned prior art correction technique of FIG. 1.